1. Technical Field
The present invention relates to a capacitor for a semiconductor device and, more specifically, to a capacitor having a metal-insulator-metal (MIM) structure for a semiconductor device.
2. Description of the Related Art
An image sensor, as a kind of semiconductor device, transforms optical images into electrical signals, and can be generally classified into a charge coupled device (CCD) and a CMOS image sensor.
A CCD comprises a plurality of photo diodes arranged in the form of a matrix to transform optical signal into electrical signal, a plurality of vertical charge coupled devices (VCCDs) formed between the photo diodes to transmit charges generated in each photo diode in a vertical direction, a plurality of horizontal charge coupled devices (HCCDs) for transmitting charges transmitted from each VCCDs in a horizontal direction, and a sense amplifier for sensing charges transmitted in the horizontal direction to output electrical signals.
CCDs have complicated operational mechanism, and high power consumption. In addition, the method for manufacturing a CCD is complicated, because multiple steps of photolithography processes are required. Especially, it is difficult to integrate a CCD with other devices such as control circuits, signal processing circuits, analog/digital converter, etc., in a single chip. Such disadvantages of CCDs prohibit miniaturization of products.
In order to overcome the disadvantages of CCDs, CMOS image sensors have been recently developed as the oncoming generation of image sensor. A CMOS image sensor generally comprises MOS transistors formed in a semiconductor substrate, and peripheral circuits such as control circuits, signal processing circuits, and the like, all of which may be formed by CMOS fabrication technologies. CMOS image sensors employ a switching mode in which the MOS transistors successively detect the output of each pixel. More specifically, a CMOS image sensor comprise a photo diode and MOS transistors in each pixel, thereby successively detecting electrical signals of each pixel in a switching mode to produce an image.
CMOS image sensors have advantages such as low power consumption and relatively simple fabrication process. In addition, CMOS image sensors can be integrated with control circuits, signal processing circuits, analog/digital converter, etc., using CMOS manufacturing technologies, resulting in miniaturization of products. CMOS image sensors have been widely used in a variety of applications such as digital still camera, digital video camera, and the like.
Meanwhile, in order to improve functions of semiconductor devices as in processing multimedia applications, memory cell arrays and peripheral circuits are highly integrated in one chip, and capacitors suitable for high-speed processing of a large volume of data become the key.
In general, capacitors for semiconductor devices can be classified into two types: one is a polysilicon-insulator-polysilicon (PIP) capacitor mainly used in DRAMs (Dynamic Random Access Memories) as an analog capacitor in sub-180 nm technologies; and the other is an MIM capacitor.
However, a problem with a PIP capacitor is that polysilicon used as upper and lower electrodes has a relatively high electrical resistivity and induces a parasitic capacitance because of a depletion phenomenon. For this reason, MIM capacitors are generally formed at sub-130 nm scales.
Hereinafter, a conventional method for manufacturing a capacitor in a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for manufacturing a capacitor in a semiconductor device.
As shown in FIG. 1A, a first metal layer is deposited on a semiconductor substrate 100, and it is selectively removed by photolithography and etching processes, forming a lower electrode 110.
As shown in FIG. 1B, a dielectric layer 120 is formed on an entire surface of the semiconductor substrate 100, covering the lower electrode 110.
As shown in FIG. 1C, a second metal layer is deposited on the dielectric layer 120, and it is selectively removed by photolithography and etching processes, forming an upper electrode 130.
As shown in FIG. 1D, an interlevel dielectric layer 140 is formed over the entire surface of the semiconductor substrate 100, covering the upper electrode 130.
Next, the interlevel dielectric layer 140 is chemically and mechanically polished, in order to facilitate the subsequent process, especially a masking process. Particularly, a thickness of the interlevel dielectric layer 140 on the upper electrode 130 is controlled such that a top surface of the upper electrode 130 is not exposed, considering a minimum processing margin of the CMP (chemical mechanical polishing) process. In the above-described conventional method, the minimum thickness of the interlevel dielectric layer 140 over the upper electrode 130 is around 3000 Å, considering the above requirements including the processing margin of the CMP process.